The invention is in the field of Semiconductor-On-Insulator (SOI) devices, and relates specifically to lateral SOI devices for high-voltage and power applications.
In fabricating high-voltage power devices, tradeoffs and compromises must typically be made in areas such as breakdown voltage, size, "on" resistance and manufacturing simplicity and reliability. Frequently, improving one parameter, such as breakdown voltage, will result in the degradation of another parameter, such as "on" resistance. Ideally, such devices would feature superior characteristics in all areas, with a minimum of operational and fabrication drawbacks.
One category of power devices that has shown considerable promise uses a semiconductor (usually silicon) layer provided on an insulating layer in a lateral configuration. A typical lateral double-diffused MOS (LDMOS) transistor in an SOI configuration is shown in U.S. Pat. No. 5,059,547. Such devices, although an improvement over earlier devices, are still a compromise in terms of the tradeoff between breakdown voltage and "on" resistance.
A promising method for obtaining high voltage lateral SOI transistors is to use a structure with a buried diode for connecting the SOI layer to the underlying substrate. Such a device is shown in FIG. 1(b) in Lu et al., "HIGH VOLTAGE SILICON-ON-INSULATOR (SOI) MOSFET'S", 3rd Int. Symp. on Power Semiconductor Devices and ICs, pp. 36-39, 1991. To support high voltages, this structure uses the well-known REduction of SURface Fields (RESURF) technique developed by Appels and Vaes, whereby the drift region of the device is depleted by the underlying substrate. As with conventional bulk technology, these SOI devices use a depletion region in the substrate to support most of the applied drain potential. The buried diode in the SOI structure is necessary so that electrons generated in the depletion region can be extracted through the reverse-biased diode and flow to the drain contact. Without this path for electrons, the deep-depletion region in the substrate would collapse due to the formation of an inversion layer along the underside of the buried oxide and the breakdown voltage of the device would be severely degraded.
With the buried diode structure, most of the applied drain potential is dropped in the substrate, as opposed to more conventional fully-isolated approaches where the voltage is dropped across the buried oxide. This allows the use of thinner buried oxides and SOI thicknesses that are simpler to process. Conventionally the buried diode has been formed by etching deep, high aspect-ratio trenches through the SOI layer with subsequent refill of the trenches with a conducting material such as highly-doped polysilicon to provide an escape path to the drain contact for electrons generated in the substrate. However, this is a relatively difficult, complex, costly and time-consuming fabrication process.
Accordingly, it would be desirable to have a lateral SOI device with a buried diode having a structure which can be easily and economically manufactured. Additionally, it would be desirable to have such an SOI device in which buried doping layers can be easily incorporated in order to improve the breakdown/"on" resistance trade-off as compared to prior-art devices.